1. Field of the Invention
The present invention is related to Integrated Circuits (ICs) and, more particularly, to ICs having air dielectric wiring for reduced capacitance.
2. Background Description
Integrated circuit (IC) performance is dependent upon individual circuit performance. Individual circuit performance is dependent on the load the circuit must drive. For field effect transistor (FET) circuits, the primary load is capacitive. The primary source of the circuit load capacitance is inter-circuit wiring capacitance. Thus, IC performance can be improved by reducing wiring capacitance.
Typical IC chips with a large number of logic circuits include multiple layers of wires, called wiring layers, stacked one on top of another and separated by dielectric material. The ideal dielectric is air or, at least has the same dielectric constant as air. There are several approaches to providing an air dielectric in IC chips.